Agnisys and Axiomise Partner to Enhance Network-on-Chip Verification for AI and GPU Designs

Agnisys, a specialist in chip automation, and Axiomise, a leader in formal verification, have announced a strategic partnership. The collaboration focuses on integrating Agnisys' IDS-NoC™ for automated Network-on-Chip (NoC) generation with Axiomise's nocProve® formal verification technology. This integration is specifically aimed at improving the design and verification processes for NoC architectures used in AI, GPU, and inference chip designs. This development is particularly important for hardware engineers and system architects involved in high-performance computing and AI infrastructure. The increasing complexity of AI and GPU chips necessitates highly efficient and reliable internal communication networks (NoCs). Traditional verification methods often struggle to keep pace with this complexity, leading to potential bugs and delays. By combining automated generation with rigorous formal verification, the partnership offers a more robust approach to ensuring the correctness of these critical components. This directly impacts the stability and performance of the AI models and applications that will run on these chips. The partnership fits within the broader trend of shifting left in the development lifecycle, emphasizing early detection and prevention of errors. In the context of cloud and DevOps, this translates to building more resilient infrastructure from the ground up. The use of formal verification, which mathematically proves the correctness of a design, aligns with the demand for higher assurance in critical systems. This trend is also seen in the growing adoption of infrastructure-as-code and automated testing in software development, where the goal is to minimize human error and increase reliability through automation and rigorous validation. The increasing reliance on AI for various tasks, from data processing to autonomous systems, underscores the need for foundational hardware that is provably correct and secure. In practice, this means that chip designers can expect a more streamlined and reliable NoC development process. They should closely watch the adoption and real-world performance of this integrated solution, particularly for projects involving cutting-edge AI accelerators. The implications include potentially faster development cycles, reduced verification costs, and ultimately, more dependable hardware for AI and GPU applications. Practitioners should consider how such formal verification approaches can be integrated into their existing design flows and evaluate the benefits against their specific project requirements and risk profiles. The move towards more automated and formally verified hardware design is a critical step in scaling AI infrastructure reliably.